1. Field of the Invention
This invention relates generally to nonvolatile memory array structure and operation. More particularly, this invention relates to flash based EEPROM nonvolatile memory device structures, peripheral circuits for operating flash based EEPROM nonvolatile memory devices and methods for operation of flash based EEPROM nonvolatile memory devices.
2. Description of Related Art
Nonvolatile memory is well known in the art. The different types of nonvolatile memory include Read-Only-Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), NOR Flash Memory, and NAND Flash Memory. In current applications such as personal digital assistants, cellular telephones, notebook and laptop computers, voice recorders, global positioning systems, etc., the Flash Memory has become one of the more popular types of Nonvolatile Memory. All EEPROM, NOR and NAND flash are Electrically Erasable and Programmable Memory using a single low-voltage power supply VDD but only EEPROM offers an erase size in unit of bytes and page with 1 M program/erase cycles.
The Flash Memory structures known in the art employ a charge retaining mechanism such as a charge storage phenomena and a charge trapping phenomena. The charge storage mechanism, as with a floating gate nonvolatile memory, the charge representing digital data is stored on a floating gate of the device. The stored charge modifies the threshold voltage of the floating gate memory cell determine that digital data stored. In a charge trapping mechanism, as in a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type cell, the charge is trapped in a charge trapping layer between two insulating layers. The charge trapping layer in the SONOS/MONOS devices has a relatively high dielectric constant (k) such Silicon Nitride (SiNx).
NOR flash provides a fast random-access, asynchronous read, but NAND flash offers a slow serial-access, synchronous read. NOR flash is the high pin-count memory chip with multiple external address and data pins, and control signal pins. One disadvantage of NOR flash is as the density being doubled, the number of its required external pin count would increase by one due to the adding of one more external address pin. In contrast, NAND has advantage of less pin-count than NOR with no address input pins. As density increases, NAND's pin count is always kept constant. Both today's NAND and NOR flash provide the advantage of in-system program and erase capabilities with 100K endurance cycles spec. NOR flash is used to store fast program code but NAND is used to store huge slow serial audio and video data storage. The size of the memory units that are erased in a NOR and NAND flash is presently around 1M bits in a giga-bit density memory device. Alternately, an EEPROM provides a unit of erase that is capable of storing a byte and a page, to permit alteration of small quantities of data or parameters.
Up until 2008, the EEPROM designs were based on a semiconductor manufacturing process where the transistor devices had a drain-to-source breakdown voltage (BVDS) of approximately ±16V. In 2008, the semiconductor manufacturing processing moved to having feature sizes less than 0.13 μm. The current EEPROM design employ program and erase voltage levels of approximately +15.0V. The current EEPROM memory cell is designed having a polycrystalline silicon floating-gate placed over a tunneling oxide. A polycrystalline control gate is formed over an inter-polycrystalline silicon oxide layer above the floating gate. Low current Fowler-Nordheim channel erase operation is used to increase the threshold voltage Vt of the memory cell above the desired value of +2.0V to store a digital datum of a logical “1”. A low-current Fowler-Nordheim channel program operation is used to decrease threshold voltage Vt of the memory cell to a voltage level of approximately −2.0V to store digital datum of a logical “0”.
The advantage of an EEPROM memory device is its high 1M program/erase cycles and its ability to be programmed in units of byte and page. However, a disadvantage of an EEPROM memory device is that the physical size of a memory cell is very large and not scalable. The averaged cell size is more than 80 λ2 and because of the inability to be scaled the manufacturing technology is employing feature sizes of approximately 0.18μ. And as noted above, the EEPROM designs were based on a drain-to-source breakdown voltage (BVDS) of approximately ±16V.